1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit for a low-voltage circuit, which is applied to a semiconductor integrated circuit (IC), and more specifically, to an ESD protection circuit using a silicon controlled rectifier (SCR).
2. Discussion of Related Art
An electrostatic discharge (ESD) phenomenon, which causes the instantaneous application of a high voltage due to static electricity that is induced by contact with a human body, frequently occurs during the fabrication or use of semiconductor components or electronic products. When a high voltage is applied to a semiconductor integrated circuit (IC) due to the ESD phenomenon, the semiconductor IC may be adversely affected or incapable of functions. For example, a thin insulating layer may be broken. Accordingly, the semiconductor IC should be designed in due consideration of the ESD phenomenon.
Above all, when a complementary metal-oxide-semiconductor (CMOS), which is very susceptible to a high voltage, is fabricated on the scale of deep submicrons (DSM), a gate oxide layer is further thinned out. Therefore, it is probable that damage caused by the ESD phenomenon will become greater.
In general, an ESD protection circuit, which is applied to a semiconductor IC, is configured such that a high voltage or current input through an input terminal is discharged through a discharge path before it is sent to core circuits.
FIG. 1 is a cross-sectional view of a gate grounded NMOS (ggNMOS) device, which is an example of a conventional ESD protection circuit.
Referring to FIG. 1, lightly doped drain (LDD)-type n+ source 2 and drain 3 are formed in a p-type semiconductor substrate 1, and a gate 5 is formed on the semiconductor substrate 1 between the source 2 and the drain 3 and electrically insulated from the semiconductor substrate 1 by a gate insulating layer 4. A silicide layer 6 is formed on the surfaces of the gate 5, the source 2, and the drain 3 to reduce contact resistance, and the source 2 and the drain 3 are connected to input/output pads S and D. In the above-described NMOS transistor, all the terminals except the drain 3 (i.e., the gate 5 and the source 2) are connected to a ground 7, and an ESD pulse is applied through the input/output pad D connected to the drain 3.
An ESD protection circuit, which is used in the above-described ggNMOS device, is comprised of an NPN bipolar transistor Q1 that includes the source 2, the semiconductor substrate 1, and the drain 3, and a substrate resistor R1.
Such an ESD protection circuit has a good ESD protection effect owing to low trigger voltage and snapback characteristics. However, because the ESD protection circuit has insufficient current discharge capacity, its size should be enlarged to obtain a reliable ESD protection effect. The larger the ESD protection circuit is, the greater a parasitic capacitance element is. Therefore, the ESD protection circuit degrades driving capability and cannot be highly integrated.
In recent years, an ESD protection circuit using a silicon controlled rectifier (SCR) has been developed. As is known, the SCR has an excellent protection function and includes only a small parasitic capacitance element. In addition, the SCR has attracted considerable attention as a device appropriate for high-speed small-sized semiconductor ICs.
FIG. 2 is a cross-sectional view of a conventional ESD protection circuit using an SCR, and FIG. 3 is an equivalent circuit diagram of the ESD protection circuit shown in FIG. 2.
Referring to FIG. 2, a p-well 12 is formed in a p+-type semiconductor substrate 11, and an n-well 13 is formed in a predetermined portion of the p-well 12. An n+ region 14a and a p+ region 15a are formed in an upper portion 8 of the n-well 13, and an n+ region 14b and a p+ region 15b are formed in an upper portion 9 of the p-well 12. The n+ region 14a and the p+ region 15a are used as an anode A, and the n+ region 14b and the p+ region 15b are used as a cathode C.
Accordingly, the p+ region 15a, the n-well 13, and the p-well 12 constitute a PNP bipolar transistor Q11, and the n-well 13, the p-well 12, and the n+ region 14b constitute an NPN bipolar transistor Q12. The SCR is comprised of the PNP bipolar transistor Q11 and the NPN bipolar transistor Q12. A resistor R11a is a resistance element of the n-well 13, a resistor R11b is a resistance element of the p+-type semiconductor substrate 11, and a resistor R11c is a resistance element of the p-well 12.
The above-described ESD protection circuit using the SCR has even greater discharge capacity than the ggNMOS device because the PNP and NPN bipolar transistors Q11 and Q12 form a positive feedback loop. Therefore, the ESD protection circuit using the SCR can obtain an effective ESD protection effect even with a small area and is suitable for a high-frequency device by minimizing a parasitic capacitance element.
However, since a trigger (driving) voltage of the SCR is as high as about 20 to 30 V, when it is applied to a metal oxide semiconductor field effect transistor (MOSFET) that is fabricated on the DSM scale, it is difficult to effectively remove an ESD pulse before a gate oxide layer is broken. In other words, an IC that is fabricated on the DSM scale cannot endure even a voltage that is far lower than 20 V. For this reason, when the ESD pulse is applied to the IC, the gate oxide layer of the MOSFET that constitutes a core circuit may be broken.